master clock
英 [ˈmɑːstə(r) klɒk]
美 [ˈmæstər klɑːk]
网络 主时钟; 主钟; 主时钟系统; 主控时钟; 母钟
双语例句
- When the body's master clock can synchronize functioning of all its metabolic, cardiovascular and behavioral rhythms in response to light and other natural stimuli, it 'gives us an edge in daily life,' Dr. Kay says.
凯博士表示，人体生物主钟在让新陈代谢、心血管和行为节奏功能与光及其它自然刺激同步的时候，也给我们的日常生活带来了点好处。 - How Its Internal Clock Is Read, Knows Reindeer Humans are pegged to a 24-hour cycle. We're locked into it not just by day and night& there's the master timepiece in the brain called the circadian clock.
人类被限制在24小时的循环内，不仅仅是被日夜限制其中，大脑中还有一种叫昼夜节律钟的计时器约束着我们。 - HD2 use one crystal oscillator for USB-interface and one crystal oscillator for master clock.
HD2给USB界面使用了一枚晶振，给主时钟使用了一枚晶振。 - The number of pulses per second produced by the master clock.
主时钟每秒产生的脉冲数。 - The serial interface operates in internal clocking ( master) mode, the AD7721 providing the serial clock.
串行接口在内部时钟（主）模式下工作，AD7721提供所需的串行时钟。 - The release of ACTH by the pituitary gland at the base of the brain is driven by a third hormone that is activated by the body's master clock.
身体的主时钟基础状态下激活另外一种激素刺激由脑垂体释放ACTH。 - In mammals, including humans, a master clock in the brain and subordinate clocks found in organs throughout the body coordinate daily, or circadian, rhythms of behavior and physiology.
在哺乳动物动物中，包括人类，在脑中有一个主时钟和在器官中发现次级时钟，协调每天的行为和生理节律。 - Research on Control Algorithm to Optimal Master Clock of Clock Synchronization in EPA Networked Control Systems
EPA网络控制系统时钟同步主时钟控制算法研究 - The normal idea to make up a digital controled oscillator ( DCO) of the digital phase locked loop ( DPLL) is to delete the pulses unwanted It need that the master clock frequency must be more faster than the output frepuency of the DPLL.
传统的数字锁相环（DPLL）多采用吞脉冲的方法来实现DCO，此方法要求工作频率远高于DPLL的输出频率。 - The master clock can be asynchronous with PCM data side clock or ADPCM data side clock. Using an 8-depth async FIFO solves the synchronization and exchange of data be-tween different clock domains.
主时钟与PCM数据端时钟或ADPCM数据端时钟可以是异步的，不同的时钟控制范围内的数据同步或交换是通过一个深度为8的FIFO来实现的； - The paper expounds the basic method and techniques of designing realtime communication software of master computer with PLC by Borland C++, including initialization, transmitting and receiving of message, communication test and error processing, time clock and timeout processing, etc..
论述了使用Borlandc＋＋设计上位微机与PLC实时通信软件的基本方法和技术，包括初始化、发送接收信息、通信测试及出错处理、定时时钟及超时处理等内容。 - The test results showed that maximum master clock frequency up to 3 MHz and greater or equal 166 ns pulse width valid.
测试结果表明：该模数转换器的最高工作时钟频率可达3MHz；工作时钟的脉冲宽度只要不小于166ns就是有效的。 - This essay mainly introduced electric time synchronous net-form mode, the basic concept and the determinant of GPS system. The basic technical need of substation GPS master clock is briefly summarized.
主要介绍了电力时间同步组网模式、GPS系统的基本概念及其决定因素，并对变电站GPS主时钟的基本技术要求作了简短小结。 - Because the same master clock is used in sampling circuit, phase alignment isn't needed, and the circuit design can be simplified.
由于采用同一主时钟对数据抽样，不需要进行相位校准，简化了电路的设计； - In the TT-FPS scheduler, firstly, the master node should send synchronization message, which also introduces time-triggered mode, to set up the uniform clock benchmark in the system.
TT-FPS调度器中主节点首先通过时间触发的方式发送同步消息，建立整个系统的统一时间基准，在接收到同步消息后，主/从节点各自均以事件触发的方式控制待传输消息发送任务的执行。 - The level difference of these re-sults at SO is a main reflection of the level difference of UTC master clock.
So结果的水平差异主要是协调世界时主钟水平差异的反映； - However, these measurements are based on local clocks, and errors resulting from differences in the rates of the master and the transparent clock devices affect the synchronization accuracy.
但是这些测量是基于本地时钟的，由于主时钟和透明时钟设备可能存在频率方面的差异，这就会带来误差，从而影响同步的精度。 - Firstly, the synchronous Ethernet mode is introduced, and the synchronous precision of the master clock and the slave one is reached to sub-nanoseconds.
首先对同步以太网模式做了介绍，并实际测量了主从时钟时间同步精度可达到亚纳秒量级。 - This paper firstly outlines the basic concepts of time synchronization and development of time synchronization technology, then analyzes and researches the PTP clock synchronization communication mechanism, best master clock algorithm, as well as the PTP messaging and internal events in a comprehensive systematic way.
本文首先概述了时间同步的基本概念以及时间同步技术的发展，其次对PTP协议中时钟同步的通信机制、最佳主时钟算法以及PTP报文的收发流程进行了全面系统地分析和研究。 - Finally, the master clock and slave one are linked by the hub or switch, the time synchronous precision is researched.
最后，通过使用集线器与交换机连接主从时钟，分析了其对同步精度的影响，可达到亚微秒的同步精度。 - Finally, after the master being selected, other clock nodes can synchronize to the master through transmitting and receiving messages.
最后，网络时钟同步系统的主时钟选举出来后，其它的时钟节点就可以通过网络传送的时钟报文同步于此主时钟。 - Best master clock algorithm is used to decide whether the PTP clock is master clock or slave clock in the thesis.
本文根据最佳主时钟算法确定PTP时钟是主时钟还是从时钟。 - We designed an IP core of SPI protocol, which could be configured as SPI Master or SPI Slave, could set different transmission speed, and could work in any one of the four clock modes.
本项目设计了一种可配置为Master或Slave模式，可设置通信速率并能适用于不同传输模式的SPI协议IP核。